best vlsi thesis

VLSI Research Topics Ideas [MS PhD]

List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

• High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
• Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
• ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
• Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
• VLSI mask optimization: From shallow to deep learning
• Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
• A Novel High-Performance Hybrid Full Adder for VLSI Circuits
• PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
• Testing single via related defectsin digital VLSI designs
• An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
• VLSI Implementation of Multi-channel ECG Lossless Compression System
• A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
• Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
• Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
• Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
• A New 4-2 Compressor for VLSI Circuits and Systems
• An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
• Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
• Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
• A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
• High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
• Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
• Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
• Fast Auto-Correction algorithm for Digital VLSI Circuits
• Review of VLSI Architecture of Cryptography Algorithm for IOT Security
• The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
• Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
• VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
• Fully Reused VLSI Architectu Encoding for DSRC Applica
• VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
• Design and vlsi implementation of a decimation filter for hearing aid applications
• Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
• A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
• Study and Analysis of Digital Counters for VLSI Applications
• Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
• VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
• Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
• Multiple-Criteria Decision Analysis Using VLSI Global Routing
• Performance Evaluation of VLSI Implemented WSN Algorithms
• Soft Error Rate Estimation of VLSI Circuits
• Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
• Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
• 2021 IEEE 39th VLSI Test Symposium (VTS)
• A spike based learning neuron in analog VLSI
• Computing Orientation of an Image by Projection Method and its VLSI Implementation
• A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
• The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
• Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
• Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
• Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
• DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
• Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
• Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
• Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
• Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
• On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
• Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
• Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
• Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
• An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
• Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
• Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
• Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
• Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
• A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
• Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
• Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
• Reconfigurable Database Processor for Query Acceleration on FPGA
• Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
• ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
• Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
• Shutdown mode implementation for Boost and Inverting Buck-Boost converter
• AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
• Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
• Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
• ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
• An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
• Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
• Laser beam testing of finished integrated circuits
• A survey of in-spin transfer torque mram computing
• Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
• Power Efficient Bit Lines: A Succinct Study
• Introduction: Soft Error Modeling
• Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
• Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
• Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
• IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
• Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
• Qualitative and quantitative analysis of parallel-prefix adders
• 4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
• Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
• BiPart: a parallel and deterministic hypergraph partitioner
• Dealing with Aging and Yield in Scaled Technologies
• Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
• A Low Power Approach for Designing 12-Bit Current Steering DAC
• Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
• Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
• Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
• A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
• Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
• A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
• Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
• Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
• Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
• An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
• Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
• A Novel Modeling-Attack Resilient Arbiter-PUF Design
• Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
• Parallel algorithms
• Transistor self-heating: The rising challenge for semiconductor testing
• Adaptive Forward Body Bias Voltage Generator
• PVT Aware Analysis of ISCAS C17 Benchmark Circuit
• Hard-to-Detect Fault Analysis in FinFET SRAMs
• Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
• Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
• Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
• Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
• High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
• Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
• Design and Analysis of 10T SRAM Cell with Stability Characterizations
• Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
• Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
• A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
• [HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
• A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
• A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
• Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
• Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
• Synchronization of mutual coupled fractional order one-sided lipschitz systems
• Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
• Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
• High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
• High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
• Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
• Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
• Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
• Machine-learning-based self-tunable design of approximate computing
• A novel current-controlled memristor-based chaotic circuit
• Performance Analysis of MoS2FET for Electronic and Spintronic Application
• Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
• Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
• New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
• Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
• Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
• On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
• Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
• HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
• A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
• Design of a new BUS for low power reversible computation
• Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
• Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
• Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
• A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
• Game Theory-based Parameter-Tuning for Path Planning of UAVs
• A Low Latency Stochastic Square Root Circuit
• New Resistorless FDNR Simulation Configuration Employing CDDITAs
• An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
• Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
• Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
• Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
• Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
• A non-autonomous chaotic system with no equilibrium
• SIXOR: Single-Cycle In-Memristor XOR
• Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
• Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
• HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
• GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
• Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
• A novel ultra-low power 7T full adder design using mixed logic
• Reversible Fade Gate as Decoder, Encoder and Full Adder
• A novel parallel prefix adder for optimized Radix-2 FFT processor
• Smart Soldier Health Monitoring System Incorporating Embedded Electronics
• Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
• Design of Efficient Ternary Subtractor
• Novel CDDITA-Based-Grounded Inductance Simulation Circuits
• Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
• Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
• Design and Analysis of Low-Power SRAM
• High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
• Selective Flip-Flop Optimization for Circuit Reliability
• Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
• Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
• Creating Fastest Self timing Reference Path for High Speed Memory Designs
• Blockchain-enabled traceable, transparent transportation system for blood bank
• Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
• Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
• Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
• Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
• Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
• Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
• Fundamentals of microelectronics
• Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
• Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
• 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
• Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
• A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
• FPGA implementation of fast digital FIR and IIR filters
• Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
• A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
• Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
• Error-Controlling Technique in Wireless Communication
• Human Action Recognition Using a New Hybrid Descriptor
• Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
• Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
• Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
• Physical synthesis for advanced neural network processors
• A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
• On the Best-Partition Communication Complexity
• IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
• Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
• Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
• Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
• Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
• Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
• A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
• PAPR Reduction in OFDM for VLC System
• A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
• FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
• Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
• A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
• AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
• Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
• A PVT aware differential delay circuit and its performance variation due to power supply noise
• A Survey on Methodologies and Database Used for Facial Emotion Recognition
• A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
• Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
• MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
• Automated Simulator for the Validation of Bio-Impedance Devices
• The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
• An Optimal Design of 16 Bit ALU
• Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
• Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
• ASSURE: RTL Locking Against an Untrusted Foundry
• Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
• Performance Analysis of Speck Cipher Using Different Adder Architectures
• A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
• Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
• Design and implementation of current mode circuit for digital modulation
• SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
• A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
• An automated parallel simulation flow for cyber-physical system design
• Conformal Omni Directional Antenna for GPS Applications
• Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
• SPIDER-based out-of-order execution scheme for Ht-MPSOC
• Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
• Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
• Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
• Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
• COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
• Design of Electronic Instrumentation for Isotope Processing
• Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
• Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
• Compact and efficient structure of 8-bit S-box for lightweight cryptography
• Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
• Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
• [HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
• Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
• Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
• Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
• The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
• Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
• TxSim: Modeling training of deep neural networks on resistive crossbar systems
• Automated Observability Analysis for Mixed-Signal Circuits
• Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
• Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
• [HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
• Computer Laboratory
• Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
• Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
• Phenomenological CNN model of a somatosensory effects
• Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
• Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
• 3–21 GHz broadband and high linearity distributed low noise amplifier
• 64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
• Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
• FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
• Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
• Fast shared-memory streaming multilevel graph partitioning
• Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
• Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
• Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
• Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
• Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
• Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
• Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
• All-digital built-in self-test scheme for charge-pump phase-locked loops
• FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
• Power-aware hold optimization for ASIC physical synthesis
• Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
• New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
• A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
• FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
• Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
• A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
• Monolithic 3D stacked multiply-accumulate units
• Guidance-based improved depth upsampling with better initial estimate
• Circuit and system-level aspects of phase change memory
• An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
• Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
• Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
• A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
• Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
• Design for Testability of Low Dropout Regulators
• Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
• Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
• Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
• High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
• Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
• Design of High-Speed Binary Counter Architecture for Low-Power Applications
• A Systematic Review on an Embedded Web Server Architecture
• Build-in compact and efficient temperature sensor array on field programmable gate array
• SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
• Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
• Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
• A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
• Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
• sonal communication, June 16, 1994.
• In-memory realization of SHA-2 using ReVAMP architecture
• Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
• Design and validation of an artificial neural network based on analog circuits
• Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
• The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
• A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
• [HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
• A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
• Multilevel Hypergraph Partitioning with Vertex Weights Revisited
• [HTML][HTML] The involution tool for accurate digital timing and power analysis
• Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
• Memristor based high speed and low power consumption memory design using deep search method
• Comparative Analysis of Adder for Various CMOS Technologies
• Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
• Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
• Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
• Global placement with deep learning-enabled explicit routability optimization
• Microcomputer Application in Motion Control
• Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
• Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
• Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
• A Theoretical Study of Design Rewiring Using ATPG
• FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
• Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
• Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
• Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
• [HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
• Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
• FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
• TRENDS IN DISTRIBUTED OBJECT COM-PUTING
• Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
• Introduction to Dual Mode Logic (DML)
• 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
• A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
• Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
• Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
• High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
• Dynamic workload allocation for edge computing
• Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
• A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
• A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
• A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
• Design and analysis of (5, 10) regular LDPC encoder using MRP technique
• Low-Voltage DML
• Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
• Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
• Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
• High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
• S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
• A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
• Evaluation of low power consumption network on chip routing architecture
• Tiny robots and sensors need tiny batteries—here’s how to do it
• Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
• Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
• Gradual magnetization switching via domain nucleation driven by spin–orbit torque
• TEM studies during development of a 4-megabit DRAM
• Circuit Design Using Genetic Programming: An Illustrative Study
• Machine Learning for Electronic Design Automation: A Survey
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Back propagation neural network based power estimation method for CMOS VLSI circuits

Low power vlsi design techniques: a review.

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Technologies for creating radiation-resistant VLSI

The technology of radiation-resistant CMOS VLSI is based on industrial IC technology. The design uses feedback circuits and guard rings to compensate for single effects of cosmic particles (SEE). In most critical cases, these influences in digital circuits lead to single faults (SEU), which temporarily disrupt the state of memory cells, to latching (SEL), and in the long term to a catastrophic change of state. Various space programs confirm great prospects for their use in future space structures. The article discusses the effects of using radiation-resistant CMOS technology, technology based on a silicon-on-sapphire structure, CMOS technology on an insulating substrate taking into account typical characteristics, SIMOX-SOI technology, which consists in separation by implantation of oxygen ions. In new designs of circuits, more advanced algorithms should be implemented for the future.

Machine Learning Based Power Estimation for CMOS VLSI Circuits

Abstract The authors have requested that this preprint be withdrawn due to a need to make corrections.

Abstract Nowdays, machine learning (ML) algorithms are receiving massive attention in most of the engineering application since it has capability in complex systems modelling using historical data. Estimation of power for CMOS VLSI circuit using various circuit attributes is proposed using passive machine learning based technique. The proposed method uses supervised learning method which provides a fast and accurate estimation of power without affecting the accuracy of the system. Power estimation using random forest algorithm is relatively new. Accurate estimation of power of CMOS VLSI circuits is estimated by using random forest model which is optimized and tuned by using multi-objective NSGA-II algorithm. It is inferred from the experimental results testing error varies from 1.4 percent to 6.8 percent and in terms of and Mean Square Error is 1.46e-06 in random forest method when compared to BPNN. Statistical estimation like coefficient of determination (𝑅) and Root Mean Square Error (RMSE) are done and it is proven that random Forest is best choice for power estimation of CMOS VLSI circuits with high coefficient of determination of 0.99938. and low RMSE of 0.000116.

Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Revisiting the Utility of Transmission Gate and Passtransistor Logic Styles in CMOS VLSI Design

Peculiarities of appearance and registration of the latchup in cmos vlsi under uniform pulsed laser irradiation, export citation format, share document.

43rd IEEE VLSI Test Symposium 2025

Phd thesis competition, tttc’s e. j. mccluskey best doctoral thesis 2025 award contest.

Named after  Prof. E. J. McCluskey , a key contributor to the field of test technology, the  2025 TTTC’s Doctoral Thesis Award  serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology.

TTTC’s E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor.

The contest is held in two stages: semi-finals and finals. In 2025, semi-finals will be held at the  IEEE VLSI Test Symposium  (VTS), the  IEEE European Test Symposium  (ETS), the I EEE Latin American Test Symposium  (LATS) and the  IEEE Asian Test Symposium  (ATS). At each semi-final, a jury composed of academia and industrial experts will determine the winner, and the four winners will compete against each other in the finals, held at the  International Test Conference (ITC) 2025.

Submission:  All four semi-final sites are seeking submissions from active doctoral students working on test-related topics. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results. Submissions to multiple regional sites are prohibited.

Prospective contestants must submit

• One-page (A4) summary of their thesis. One additional page is allowed for figures and references [filename: firstname_lastname_thesis].
• One/two-page resume [filename: firstname_lastname_resume].

Do not upload any other documents.

Submissions must include the names of the student, one advisor and start/end dates, and will undergo a selection process. Selected contestants will be given a short presentation slot in a designated technical session. The winner will be determined by the jury and announced during the event.

Please combine all files into a single PDF file and submit your application to the Students Activities Chair, Vidya Chhabria:   

  Submission deadline : 1 March 2025

Contact persons:

• Global coordinator: Michele Portolan ([email protected])
• VTS 2025 coordinator: Vidya Chhabria:   

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Piyush 601762013 mtech thesis...VLSI Design

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